Supported by the Crossware Development Suite for ARM Pathfinder, Developer and Professional Editions
Graphical Code Creation Wizards:
- Analog to digital converters (ADC1, ADC2 and ADC3
- CAN interfaces (CAN1 and CAN2)
- CRC engine
- Cryptographic processor
- Digital to analog converter (DAC)
- DMA controllers (DMA1 and DMA2)
- External interrupts
- FSMC
- Flash controller
- Hash processor
- I2C interfaces (I2C1 and I2C2)
- Nested vectored interrupt controller (NVIC)
- Ports
- Random number generator
- Reset and clock control
- Serial peripheral interfaces (SPI1, SPI2 and SPI3)
- Timers (Timer 1, 2, 3, 4, 5, 6, 7 and 8
- Universal asynchronous receiver/transmitters(UART4 and UART5)
- Universal synchronous/asynchronous receiver/transmitters(USART1, USART2, USART3 and USART6)
Context menu Code Creation Wizards:
- Analog to digital converters (ADC1, ADC2 and ADC3
- CAN interfaces (CAN1 and CAN2)
- CRC engine
- Cryptographic processor
- Digital to analog converter (DAC)
- DCMI
- DMA controllers (DMA1 and DMA2)
- Ethernet
- External interrupts
- Flash controller
- FSMC
- Hash processor
- I2C interfaces (I2C1 and I2C2)
- Independent watch dog
- Nested vectored interrupt controller (NVIC)
- Ports
- USB OTG FS
- PWR
- Random number generator
- Reset and clock control
- SDIO
- Serial peripheral interfaces (SPI1, SPI2 and SPI3)
- Timers (Timer 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14)
- Universal asynchronous receiver/transmitters(UART4 and UART5)
- Universal synchronous/asynchronous receiver/transmitters(USART1, USART2, USART3 and USART6)
- Windowed watch dog
jState Code Creation Wizards:
- Analog to digital converters (ADC1, ADC2 and ADC3
- CAN interfaces (CAN1 and CAN2)
- CRC engine
- Cryptographic processor
- Digital to analog converter (DAC)
- DCMI
- DMA controllers (DMA1 and DMA2)
- Ethernet
- External interrupts
- Flash controller
- FSMC
- Hash processor
- I2C interfaces (I2C1 and I2C2)
- Independent watch dog
- Nested vectored interrupt controller (NVIC)
- Ports
- USB OTG FS
- PWR
- Random number generator
- Reset and clock control
- SDIO
- Serial peripheral interfaces (SPI1, SPI2 and SPI3)
- Timers (Timer 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14)
- Universal asynchronous receiver/transmitters(UART4 and UART5)
- Universal synchronous/asynchronous receiver/transmitters(USART1, USART2, USART3 and USART6)
- Windowed watch dog
Cortex-M3 core simulation
- Instruction set simulation
- Nested vectored interrupt controller(NVIC) including SysTick
- Bit-banding to and from SRAM
Peripheral simulation:
Register views:
- Core
- ADCs/EXTI
- CAN/Flash
- Ports
- I2Cs
- PWR
- RCC
- SPIs
- Timers
- USARTs
- SDIO
- Watchdogs
- NVIC
- FSMC
- CRC/DAC
- OTG FS
- CRYPT/HASH/RNG
- Ethernet
- DCMI
- DMA
Source level on-chip debugging with Jaguar USB JTAG interface