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MICROPROCESSOR INSTRUCTION REFERENCE->Integer Arithmetic Instructions


InstructionOperand
Syntax
Operand
Size
Operation
ADDDn,<ea>
<ea>,Dn
32Source+Destination->Destination
ADDA<ea>,An32Source+An->An
ADDI#<data>,Dn32<data>+Dn->Dn
ADDQ#<data>,<ea>32<data>+Destination -> Destination
ADDXDy,Da32Dy+Dx+X -> Dx
CLR<ea>8,16,320 -> Destination
CMP<ea>,Dn32Dn  Source
CMPA<ea>,An32An  Source
CMPI#<data>,Dn8,16,32Dn - <data>
EXTDn8->16
16->32
Sign extend Dn
EXTBDn8->32Sign extend Dn
MULS<ea>,Dn16*16->32
32*32->32
Source * Dn -> Dn (signed)
MULU<ea>,Dn16*16->32
32*32->32
Source * Dn -> Dn (unsigned)
NEG<ea>320  Destination -> Destination
NEGX<ea>320  Destination - X-> Destination
SUB<ea>,Dn
Dn,<ea>
32Destination  Source -> Destination
SUBA<ea>,An32An  Source -> An
SUBI#<data>,Dn32Dn - <data> -> Dn
SUBQ#<data>,<ea>32Destination - <data> -> Destination
SUBXDy,Dx32Dx  Dy  X -> Dx
    

For chips with a divide unit (CF5206e and CF5307):
    
InstructionOperand
Syntax
Operand
Size
Operation
DIVS<ea>,Dn32/16->16
32/32->32
Source / Dn -> 16r:16q (signed)
Source /Dn -> Dn (signed)
DIVU<ea>,Dn32/16->16
32/32->32
Source * Dn -> 16r:16q (unsigned)
Source / Dn -> Dn (unsigned)
REMS<ea>,Dn32%32->32Source % Dn -> Dn (signed)
REMU<ea>,Dn32%32->32Source % Dn -> Dn (unsigned)