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MICROPROCESSOR INSTRUCTION REFERENCE->DIVU

DIVU    Unsigned Divide

Compatibility:    Starting with 5206e.

Destination/Source -> Destination
    

Assembler Syntax:	DIVU.W <ea>,Dn	32/16 -> 16r:16q
	DIVU.L <ea>,Dq	32/32 -> 32q

Size:    Word, Long

For word size, divides the 32 bit unsigned destination operand by the 16 bit unsigned source operand and stores the 16 unsigned quotient and the 16 bit unsigned remainder result in the destination.  The quotient is stored in the lower word of the destination and the remainder is stored in the upper word of the destination.  An overflow occurs is the quotient is larger than a 16 bit unsigned integer.

For long size, divides the 32 bit unsigned destination operand by the 32 bit unsigned source operand and stores the 32 unsigned quotient in the destination. An overflow occurs is the quotient is larger than a 32 bit unsigned integer.

Division by zero causes a divide-by-zero exception with the exception stack frame pointing to the faulting DIVU instruction.


Condition Codes:
    
N    Cleared if overflow detected, else set if quotient is negative and cleared if quotient is positive
Z    Cleared if overflow detected, else set if quotient is zero and cleared if quotient is nonzero
V    Set if overflow, else cleared
C    Always cleared
X    Not affected

    

Allowable Addressing Modes

    

	DIVU.W	Dn,Dn	DIVU.L	Dn,Dn
	DIVU.W	(An),Dn	DIVU.L	(An),Dn
	DIVU.W	(An)+,Dn	DIVU.L	(An)+,Dn
	DIVU.W	-(An),Dn	DIVU.L	-(An),Dn
	DIVU.W	(d16,An),Dn	DIVU.L	(d16,An),Dn
	DIVU.W	(d8,An,Xn),Dn
	DIVU.W	(xxx).L,Dn
	DIVU.W	(xxx).L,Dn
	DIVU.W	#<data>,Dn
	DIVU.W	(d16,PC),Dn
	DIVU.W	(d8,An,Xn),Dn