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MICROPROCESSOR INSTRUCTION REFERENCE->DIVU

DIVU    Unsigned Divide
DIVUL

Compatibility: 68000, 68010, 68020 and CPU32 families.

Destination/Source -> Destination

Assembler Syntax:	DIVU.W <ea>,Dn	32/16 -> 16r:16q
	1DIVU.L <ea>,Dq	32/32 -> 32q
	1DIVU.L <ea>,Dr:Dq	64/32 -> 32r:32q
	1DIVUL.L <ea>,Dr:Dq	32/32 -> 32r:32q

1   68020 only

Size:    Word, Long

Divides the unsigned destination operand by the unsigned source operand and stores the unsigned result in the destination.  For word size, overflow occurs if the quotient is larger than a 16 bit signed integer.  For long size, overflow occurs if the quotient is larger than a 32 bit unsigned integer.  If an overflow is detected, the operands are unaffected.

Condition Codes:

N    Set if quotient -ve, else cleared but undefined if overflow or divide by zero
Z    Set if quotient = 0, else cleared but undefined if overflow or divide by zero
V    Set if overflow, else cleared but undefined if divide by zero
C    Always cleared
X    Not affected

    

	Allowable Addressing Modes

	DIVU	Dn,Dn	DIVU.L   Dn,Dr:Dq
	DIVU	(An),Dn	DIVU.L   (An),Dr:Dq
	DIVU	(An)+,Dn	DIVU.L   (An)+,Dr:Dq
	DIVU	-(An),Dn	DIVU.L   -(An),Dr:Dq
	DIVU	(d16,An),Dn	DIVU.L   (d16,An),Dr:Dq
	DIVU	(d8,An,Xn),Dn	DIVU.L   (d8,An,Xn),Dr:Dq
	DIVU	(bd,An,Xn),Dn 2	DIVU.L   (bd,An,Xn),Dr:Dq 2
	DIVU	([bd,An,Xn],od),Dn 1	DIVU.L   [bd,An,Xn],od),Dr:Dq 1
	DIVU	([bd,An],Xn,od),Dn 1	DIVU.L   [bd,An],Xn,od),Dr:Dq 1
	DIVU	(xxx).W,Dn	DIVU.L   (xxx).W,Dr:Dq
	DIVU	(xxx).L,Dn	DIVU.L   (xxx).L,Dr:Dq
	DIVU	#(data),Dn	DIVU.L   #(data),Dr:Dq
	DIVU	(d16,PC),Dn	DIVU.L   (d16,PC),Dr:Dq
	DIVU	(d8,PC,Xn),Dn	DIVU.L   (d8,PC,Xn),Dr:Dq
	DIVU	(bd,PC,Xn),Dn 2	DIVU.L   (bd,PC,Xn),Dr:Dq 2
	DIVU	([bd,PC,Xn],od),Dn 1	DIVU.L   ([bd,PC,Xn],od),Dr:Dq 1
	DIVU	([bd,PC],Xn,od),Dn 1	DIVU.L   ([bd,PC],Xn,od),Dr:Dq 1

1   68020 only
2   68020 and CPU32 only

See DIVUL for DIVUL addressing modes.