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MICROPROCESSOR INSTRUCTION REFERENCE->DIVSL
DIVSL Signed Divide
Compatibility: 68020 and CPU32 families only.
Size: Long
| Allowable Addressing Modes |
| DIVSL.L | Dn,Dr:Dq | |
| DIVSL.L | (An),Dr:Dq | |
| DIVSL.L | (An)+,Dr:Dq | |
| DIVSL.L | -(An),Dr:Dq | |
| DIVSL.L | (d16,An),Dr:Dq | |
| DIVSL.L | (d8,An,Xn),Dr:Dq | |
| DIVSL.L | (bd,An,Xn),Dr:Dq | |
| DIVSL.L | ([bd,An,Xn],od),Dr:Dq 1 | |
| DIVSL.L | ([bd,An],Xn,od),Dr:Dq 1 | |
| DIVSL.L | (xxx).W,Dr:Dq | |
| DIVSL.L | (xxx).L,Dr:Dq | |
| DIVSL.L | #(data),Dr:Dq | |
| DIVSL.L | (d16,PC),Dr:Dq | |
| DIVSL.L | (d8,PC,Xn),Dr:Dq | |
| DIVSL.L | (bd,PC,Xn),Dr:Dq | |
| DIVSL.L | ([bd,PC,Xn],od),Dr:Dq 1 | |
| DIVSL.L | ([bd,PC],Xn,od),Dr:Dq 1 |