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MICROPROCESSOR INSTRUCTION REFERENCE->DIVS

DIVS    Signed Divide
DIVSL

Compatibility: 68000, 68010, 68020 and CPU32 families.

Destination/Source -> Destination

Assembler Syntax:	DIVS.W <ea>,Dn	32/16 -> 16r:16q
	1DIVS.L <ea>,Dq	32/32 -> 32q
	1DIVS.L <ea>,Dr:Dq	64/32 -> 32r:32q
	1DIVSL.L <ea>,Dr:Dq	32/32 -> 32r:32q

1   68020 and CPU32 only

Size:    Word, Long

Divides the signed destination operand by the signed source operand and stores the signed result in the destination.  For word size, overflow occurs if the quotient is larger than a 16 bit signed integer.  For long size, overflow occurs if the quotient is larger than a 32 bit signed integer.  If an overflow is detected, the operands are unaffected.

Condition Codes:

N    Set if quotient -ve, else cleared but undefined if overflow or divide by zero
Z    Set if quotient = 0, else cleared but undefined if overflow or divide by zero
V    Set if overflow, else cleared but undefined if divide by zero
C    Always cleared
X    Not affected

    

	Allowable Addressing Modes

	DIVS	Dn,Dn	DIVS.L	Dn,Dr:Dq
	DIVS	(An),Dn	DIVS.L	(An),Dr:Dq
	DIVS	(An)+,Dn	DIVS.L	(An)+,Dr:Dq
	DIVS	-(An),Dn	DIVS.L	-(An),Dr:Dq
	DIVS	(d16,An),Dn	DIVS.L	(d16,An),Dr:Dq
	DIVS	(d8,An,Xn),Dn	DIVS.L	(d8,An,Xn),Dr:Dq
	DIVS	(bd,An,Xn),Dn 2	DIVS.L	(bd,An,Xn),Dr:Dq 2
	DIVS	([bd,An,Xn],od),Dn 1	DIVS.L	([bd,An,Xn],od),Dr:Dq 1
	DIVS	([bd,An],Xn,od),Dn 1	DIVS.L	([bd,An],Xn,od),Dr:Dq 1
	DIVS	(xxx).W,Dn	DIVS.L	(xxx).W,Dr:Dq
	DIVS	(xxx).L,Dn	DIVS.L	(xxx).L,Dr:Dq
	DIVS	#(data),Dn	DIVS.L	#(data),Dr:Dq
	DIVS	(d16,PC),Dn	DIVS.L	(d16,PC),Dr:Dq
	DIVS	(d8,PC,Xn),Dn	DIVS.L	(d8,PC,Xn),Dr:Dq
	DIVS	(bd,PC,Xn),Dn 2	DIVS.L	(bd,PC,Xn),Dr:Dq 2
	DIVS	([bd,PC,Xn],od),Dn 1	DIVS.L	([bd,PC,Xn],od),Dr:Dq 1
	DIVS	([bd,PC],Xn,od),Dn 1	DIVS.L	([bd,PC],Xn,od),Dr:Dq 1

1   68020 only
2   68020 and CPU32 only

See also DIVSL.