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MICROPROCESSOR INSTRUCTION REFERENCE->OTDMR
OTDMR Output memory indirectly addressed by HL to port (C) decrementing HL and C and decrementing B. Until B=0
(C) <- (HL) : HL <- HL-1
C <- C-1 : B <- B-1
C to A0-A7
0 to A8-A15
Flags
S | Cleared Always |
Z | Set always |
H | Cleared Always |
P/V | Set always |
N | Set to MSB of data |
C | Cleared Always |
No of | M | T | usec @ | |
bytes | cycles | states | 2 MHz |
B<>0 | 2 | 8 | 16 | 8 |
B=0 | 2 | 6 | 14 | 7 |