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MICROPROCESSOR INSTRUCTION REFERENCE->OTDR

OTDR  Output memory indirectly address by HL to port (C) and decrement B and HL Repeat until B=0

(C) <- (HL) : B <- B-1 : HL <- HL_1

                        C to A0-A7
                        B to A8-A15

Flags
    

S	Unknown
Z	Set always (on completion)
H	Unknown
P/V	Unknown
N	Set always
C	Unknown

    

	No of	M	T	usec @
	bytes	cycles	states	2 MHz

B<>0	2	5	21	10.5
B=0	2	4	16	8