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MICROPROCESSOR INSTRUCTION REFERENCE->OTIM

OTIM  Output memory indirectly addressed by HL to port (C) incrementing HL and C and decrementing B

(C) <- (HL) : HL <- HL+1
C <- C+1    : B <- B-1
                        C to A0-A7
                        0 to A8-A15

Flags
    

S	Set if result -ve, else cleared
Z	Set if B becomes 0, else cleared
H	Set if half carry, else cleared
P/V	Set if parity even, else cleared
N	Set to MSB of data
C	Set if carry, else cleared

    

No of	M	T	usec @
bytes	cycles	states	2 MHz

2	6	14	7
HD64180 only      <Return> for OTIMR