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MICROPROCESSOR INSTRUCTION REFERENCE->FNEG

Floating-Point Negate

Compatibility: ColdFire chips with a floating-point unit (FPU)

-Source -> FPx

    

Assembler Syntax:	FNEG.fmt <ea>,FPx
	FNEG.D FPy,FPx
	FNEG.D FPx
	FrNEG.fmt <ea>,FPx
	FrNEG.D FPy,FPx
	FrNEG.D FPx

where r is rounding precision, S or D

Format: Byte (B), Word (W), Long (L), Single-precision (S), Double-precision (D)

Converts the source operand to double-precision (if necessary) and inverts the sign of the mantissa.  Stores the result in the destination floating point data register.

FSNEG rounds to single-precision, FDNEG rounds to double-precision and FNEG rounds to the precision specified by the floating point control register FPCR (which by default is double-precision).

Floating-Point Status Register:

N	Set if result is negative;else cleared
Z	Set if result is zero;else cleared
I	Set if result is infinity;else cleared
NAN	Set if result is a NAN;else cleared
BSUN	Always cleared
INAN	Set if the input is not-a-number; else cleared
IDE	Set if the input is a denormalised number; else cleared
OPERR	Always cleared
OVFL	Always cleared
UNFL	Always cleared
DZ	Always cleared
INEX	Always cleared

    

	Allowable Addressing Modes

	Dn,FPn
	(An),FPn
	(An)+,FPn
	-(An),FPn
	(d16,An),FPn
	(d16,PC),FPn