Table of Contents        Previous topic       Next topic       

MICROPROCESSOR INSTRUCTION REFERENCE->FMUL

Floating-Point Multiply

Compatibility: ColdFire chips with a floating-point unit (FPU)

Source * FPx -> FPx

    

Assembler Syntax:	FMUL.fmt <ea>,FPx
	FMUL.D FPy,FPx
	FrMUL.fmt <ea>,FPx
	FrMUL.D FPy,FPx

where r is rounding precision, S or D

Format: Byte (B), Word (W), Long (L), Single-precision (S), Double-precision (D)

Converts the source operand to double-precision (if necessary) and multiplies that number into the number in the destination floating point data register.  Stores the result in the destination floating point data register.

FSMUL rounds to single-precision, FDMUL rounds to double-precision and FMUL rounds to the precision specified by the floating point control register FPCR (which by default is double-precision).

Floating-Point Status Register:

N	Set if result is negative;else cleared
Z	Set if result is zero;else cleared
I	Set if result is infinity;else cleared
NAN	Set if result is a NAN;else cleared
BSUN	Always cleared
INAN	Set if either input is not-a-number; else cleared
IDE	Set if either input is a denormalised number; else cleared
OPERR	Set if multiplying zero by infinity; else cleared
OVFL	Set if the exponent of the intermediate result is greater than or equal to the maximum exponent value for the selected rounding precision; else cleared
UNFL	Set if the intermediate result is too small to be represented by a normalised number in the selected rounding precision; else cleared
DZ	Always cleared
INEX	Set if the infinitely-precise mantissa of the intermediate result has more significant bits than can be represented exactly in the selected rounding precision; or if either input is a denormalised number and the IDE exception is disabled; or if the result overflowed; or if the result underflowed and the underflow exception is disabled; else cleared

    

	Allowable Addressing Modes

	Dn,FPn
	(An),FPn
	(An)+,FPn
	-(An),FPn
	(d16,An),FPn
	(d16,PC),FPn