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MATHS CO-PROCESSOR REFERENCE->FSGLDIV

FSGLDIV           Single Precision Divide

FPn / source -> FPn

Assembler Syntax:FSGLDIV.<fmt> <ea>,FPn
FSGLDIV.X FPm,FPn


Attributes: Byte, Word, Long, Single, Double, Extended, Packed

    
Allowable Addressing Modes
    
FSGLDIV.XFPm,FPn
FSGLDIV.<fmt> Dn,FPn  Only if <fmt> is .B,.W,.L or .S
FSGLDIV.<fmt> (An),FPn
FSGLDIV.<fmt> (An)+,FPn
FSGLDIV.<fmt> -(An),FPn
FSGLDIV.<fmt> (d16,An),FPn
FSGLDIV.<fmt> (d8,An,Xn),FPn
FSGLDIV.<fmt> (bd,An,Xn),FPn
FSGLDIV.<fmt> ([bd,An,Xn],od),FPn
FSGLDIV.<fmt> ([bd,An],Xn,od),FPn
FSGLDIV.<fmt> (xxx).W,FPn
FSGLDIV.<fmt> (xxx).L,FPn
FSGLDIV.<fmt> #(data),FPn
FSGLDIV.<fmt> (d16,PC),FPn
FSGLDIV.<fmt> (d8,PC,Xn),FPn
FSGLDIV.<fmt> (bd,PC,Xn),FPn
FSGLDIV.<fmt> ([bd,PC,Xn],od),FPn
FSGLDIV.<fmt> ([bd,PC],Xn,od),FPn