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MICROPROCESSOR INSTRUCTION REFERENCE->BCLR
BCLR Test a Bit and Clear
Compatibility: 68000, 68010, 68020, CPU32 families
Complement of (<bit no.> Destination) -> Z
0 -> (<bit no.> Destination)
| Assembler Syntax: | BCLR Dn,<ea> |
| BCLR #<data>,<ea> |
Dn or #<data> specify the bit no. and <ea> may be data alterable only
Size: Byte, Long
Tests a bit in the destination operand and sets the Z condition code appropriately, then clears the specified bit in the destination. When a data register is the destination, any of the 32 bits can be specified by a modulo 32-bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8.. In all cases, bit zero refers to the least significant bit.
If <ea> is Data register then #<data> 0 - 31 else #<data> 0 - 7
Condition Codes:
N Not affected
Z Set if bit tested = 0, else clear
V Not affected
C Not affected
X Not affected
| Allowable Addressing Modes |
|
| BCLR | Dn,Dn | BCLR | #(data),Dn |
| BCLR | Dn,(An) | BCLR | #(data),(An) |
| BCLR | Dn,(An)+ | BCLR | #(data),(An)+ |
| BCLR | Dn,-(An) | BCLR | #(data),-(An) |
| BCLR | Dn,(d16,An) | BCLR | #(data),(d16,An) |
| BCLR | Dn,(d8,An,Xn) | BCLR | #(data),(d8,An,Xn) |
| BCLR | Dn,(bd,An,Xn) 2 | BCLR | #(data),(bd,An,Xn) 2 |
| BCLR | Dn,([bd,An,Xn],od) 1 | BCLR | #(data),([bd,An,Xn],od) 1 |
| BCLR | Dn,([bd,An],Xn,od) 1 | BCLR | #(data),([bd,An],Xn,od) 1 |
| BCLR | Dn,(xxx).W | BCLR | #(data),(xxx).W |
| | BCLR | Dn,(xxx).L | BCLR | #(data),(xxx).L |
Dn,Dn and #(data),Dn are long only; all others are byte only.
1 68020 only
2 68020 and CPU32 only