Table of Contents
Previous topic Next topic
MICROPROCESSOR INSTRUCTION REFERENCE->BCHG
BCHG Test a Bit and Change
Compatibility: 68000, 68010, 68020, CPU32 families
Complement of (<bit no.> Destination) -> Z
Complement of (<bit no.> Destination) -> (<bit no.> Destination)
| Assembler Syntax: | BCHG Dn,<ea> |
| BCHG #<data>,<ea> |
Dn or #<data> specify the bit no. and <ea> may be data alterable only
Size: Byte, Long
Tests a bit in the destination operand and sets the Z condition code appropriately, then inverts the specified bit in the destination. When the destination is a data register, any of the 32 bits can be specified by the modulo 32-bit number. When the destination is a memory location, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit.
If <ea> is Data register then #<data> 0 - 31 else #<data> 0 - 7
Condition Codes:
N Not affected
Z Set if bit tested = 0, else clear
V Not affected
C Not affected
X Not affected
| Allowable Addressing Modes |
|
| BCHG | Dn,Dn | BCHG | #(data),Dn |
| BCHG | Dn,(An) | BCHG | #(data),(An) |
| BCHG | Dn,(An)+ | BCHG | #(data),(An)+ |
| BCHG | Dn,-(An) | BCHG | #(data),-(An) |
| BCHG | Dn,(d16,An) | BCHG | #(data),(d16,An) |
| BCHG | Dn,(d8,An,Xn) | BCHG | #(data),(d8,An,Xn) |
| BCHG | Dn,(bd,An,Xn) 2 | BCHG | #(data),(bd,An,Xn) 2 |
| BCHG | Dn,([bd,An,Xn],od) 1 | BCHG | #(data),([bd,An,Xn],od) 1 |
| BCHG | Dn,([bd,An],Xn,od) 1 | BCHG | #(data),([bd,An],Xn,od) 1 |
| BCHG | Dn,(xxx).W | BCHG | #(data),(xxx).W |
| | BCHG | Dn,(xxx).L | BCHG | #(data),(xxx).L |
Dn,Dn and #(data),Dn are long only; all others are byte only.
1 68020 only
2 68020 and CPU32 only