Table of Contents        Previous topic       Next topic       

MICROPROCESSOR INSTRUCTION REFERENCE->LDDR

LDDR   Load memory indirectly addressed by HL into memory indirectly addressed by DE, decrementing BC, DE and HL Repeating until BC = 0

(DE) <- (HL) : DE <- DE-1
              HL <- HL-1  
              BC <- BC-1

Flags
    

S	Not affected
Z	Not affected
H	Cleared always
P/V	Cleared always (on completion)
N	Cleared always
C	Not affected

    

	No of	M	T	usec @
	bytes	cycles	states	2 MHz

B<>0	2	5	21	10.5
B=0	2	4	16	8