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MICROPROCESSOR INSTRUCTION REFERENCE->LDD

LDD   Load memory indirectly addressed by HL into memory indirectly addressed by DE, decrementing BC, DE and HL

(DE) <- (HL) : DE <- DE-1
              HL <- HL-1  
              BC <- BC-1

Flags
    

S	Not affected
Z	Not affected
H	Cleared always
P/V	Cleared if BC becomes 0, else set
N	Cleared always
C	Not affected

    

No of	M	T	usec @
bytes	cycles	states	2 MHz

2

4

16

8