Table of Contents        Previous topic       Next topic       

MICROPROCESSOR INSTRUCTION REFERENCE->SEI

SEI    Set Interrupt Mask

This is a 6800 opcode which is translated into:

          ORCC #&10

Condition Code Register:

E  Not affected
F  Not affected
H  Not affected
I  Set cleared
N  Not affected
Z  Not affected
V  Not affected
C  Not affected

    

Addressing mode	No of cycles	No of bytes
Implied	3	2