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MICROPROCESSOR INSTRUCTION REFERENCE->SEF
SEF Set Fast Interrupt Mask
This is a 6800-like opcode which is translated into:
ORCC #&40
Condition Code Register:
E Not affected
F Set Always
H Not affected
I Not affected
N Not affected
Z Not affected
V Not affected
C Not affected
Addressing mode | No of cycles | No of bytes |
Implied | 3 | 2 |