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MICROPROCESSOR INSTRUCTION REFERENCE->LSR

LSR   Shift Accumulator or Memory Byte Right Logically
LSRA
LSRB
LSR

0 -> b7 ->....-> b0 -> C


Condition Code Register:

H  Not affected
N  Always cleared
Z  Set if result Zero, else cleared
V  Not affected
C  <- b0 of original operand

    

Addressing mode	No of cycles	No of bytes
Implied:	2	1
Direct:	6	2
Extended:	7	3
Index/Indirect:	6+	2+