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MICROPROCESSOR INSTRUCTION REFERENCE->LSL

LSL   Shift Accumulator or Memory Byte Left Logically
LSLA
LSLB
LSL   This instruction and ASL are identical

C <- b7 <- ...<- b0 <- 0

Condition Code Register:

H  Undefined
N  Set if result Negative, else cleared
Z  Set if result Zero, else cleared
V  <- b6 EOR b7 of original operand
C  <- b7 of original operand

    
Addressing modeNo of cyclesNo of bytes
Implied:21
Direct:62
Extended:73
Index/Indirect:6+2+