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MICROPROCESSOR INSTRUCTION REFERENCE->MSACL
MSACL Multiply and Subtract with Register Load
Compatibility: Starting with 5206e.
where <shift> is either << or >>, <UL> indicates that either a U or L must be used and & produces a masked operation.
|Assembler Syntax:||MSACL.W Ry.<UL>,Rx<UL>,<ea>,Rw|
Size: Word, Long
Multiply the 16 bit or 32 bit operands together to produce a 32 bit result and subtract the result optionally shifted one bit to the left or right from the contents of the MAC accumulator ACC. The result is stored back into the accumulator.
In parallel with this operation, a 32 bit operand is fetched from the memory location defined by <ea> and loaded into the destination Rw. If the mask addressing mode is used, the lower order word of <ea> is ANDed with the MAC mask register.
If 16 bit operands are used, they may be located in the upper or lower word of the register and U or L must be used to specify upper word or lower word respectively.
MAC status register:
|OMC ||Not affected|
|S/U ||Not affected|
|N||Set if the most significant bit of the result is set, else cleared|
|Z||Set if the result is zero, else cleared|
|V||Set if an overflow generated, else unchanged|
|Allowable Addressing Modes <ea>||