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PROGRAM MAINTENANCE UTILITY->Inference rules
Inference rules define how a file with on extension can be created from a file with another extension. They provide a convenient shorthand for commonly used operations.
There are predefined inference rules which are listed later and additional inference rules can be defined in the description file.
MAKE will use an inference rule in the following circumstances:
when a description block has no commands, MAKE will search for an inference rule that matches the extensions of the target and dependency files.
when a dependency line does not contain any dependency files, MAKE will search for an inference rule which tells it how to create the missing dependent filename.
when a description block has no dependency files and no commands (ie only targets are listed), MAKE will use an inference rule to create the target.
The format for an inference rule is:
.<dependent extension>.<target extension> : ;command
The first period must be at the beginning of the line with no preceding spaces.
The commands are those that which will be run if the target is out-of-date.
A command can optionally be placed after colon but must be preceded by a semi-colon.
An example of an inference rule definition is:
cl /c $*.c
This inference rule tells MAKE how to build a .OBJ file from a .C file. The predefined macro $* expands to the base name of the current target file.
A description block consisting of just:
is then sufficient for MAKE to be able to create the target sample.obj and it will use the command:
cl /c sample.c
The predefined inference rules are:
|.c.obj||cl /c $(CFLAGS) $*.c||cl /c $*.c|
|.c.||cl $(CFLAGS) $(LFLAGS) $*.c||cl $*.c|
|.asm.obj||xasm $(XFLAGS) $*;||xasm $*;|
|.asm||xl $(XFLAGS) $(LFLAGS) $*.asm||xl $*.asm|
|.obj||link $(LFLAGS) $*;||link $*;|