Table of Contents        Previous topic       Next topic       

MICROPROCESSOR INSTRUCTION REFERENCE->MULU

MULU   Unsigned Multiply

Compatibility: 68000, 68010, 68020 and CPU32 families.

Destination x Source -> Destination

Assembler Syntax:	MULU.W <ea>,Dn	16 x 16 -> 32
	1 MULU.L <ea>,Dl	32 x 32 -> 32
	1 MULU.L <ea>,Dh:Dl	32 x 32 -> 64

1   68020 and CPU32

<ea> - data

Size:  Word, Long

Multiplies two unsigned operands yielding an unsigned result.

In the word form, the multiplier and multiplicand are both word operands, and the result is a long-word operand.  A register operand is the low-order word; the upper word of the register is ignored.  All 32 bits of the product are saved in the destination data register.  

In the long form, the multiplier and multiplicand are both long-word operands, and the result is either a long word or a quad word.  The long-word result is the low-order 32 bits of the quad word result; the high-order 32 bits of the products are discarded.


Condition Codes:

N    Set if most significant bit of result is set, else cleared
Z    Set if result zero, else cleared
V    Set if overflow, else cleared
C    Always cleared
X    Not affected

    

	Allowable Addressing Modes

	<ea>,Dn (or Dl)	<ea>,Dh:Dl

	MULU	Dn,Dn	MULU	Dn,Dh:Dl
	MULU	(An),Dn	MULU	(An),Dh:Dl
	MULU	(An)+,Dn	MULU	(An)+,Dh:Dl
	MULU	-(An),Dn	MULU	-(An),Dh:Dl
	MULU	(d16,An),Dn	MULU	(d16,An),Dh:Dl
	MULU	(d8,An,Xn),Dn	MULU	(d8,An,Xn),Dh:Dl
	MULU	(bd,An,Xn),Dn 2	MULU	(bd,An,Xn),Dh:Dl 2
	MULU	([bd,An,Xn],od),Dn 1	MULU	([bd,An,Xn],od),Dh:Dl 1
	MULU	([bd,An],Xn,od),Dn 1	MULU	([bd,An],Xn,od),Dh:Dl 1
	MULU	(xxx).W,Dn	MULU	(xxx).W,Dh:Dl
	MULU	(xxx).L,Dn	MULU	(xxx).L,Dh:Dl
	MULU	#(data),Dn	MULU	#(data),Dh:Dl
	MULU	(d16,PC),Dn	MULU	(d16,PC),Dh:Dl
	MULU	(d8,PC,Xn),Dn	MULU	(d8,PC,Xn),Dh:Dl
	MULU	(bd,PC,Xn),Dn 2	MULU	(bd,PC,Xn),Dh:Dl 2
	MULU	([bd,PC,Xn],od),Dn 1	MULU	([bd,PC,Xn],od),Dh:Dl 1
	MULU	([bd,PC],Xn,od),Dn 1	MULU	([bd,PC],Xn,od),Dh:Dl 1

1   68020 only
2   68020 and CPU32 only