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MICROPROCESSOR INSTRUCTION REFERENCE->BFEXTU

BFEXTU    Extract Bit Field Unsigned

Compatibility: 68020 family only.

<bit field> of Source -> Dn

Assembler Syntax:    BFEXTU <ea>{offset:width},Dn

Unsized

Extracts the bit field from the specified effective address location, zero extends to 32 bits, and loads the results into the destination data register.

The field offset and field width select th efield.  The field offset specifies the starting bit of the field.  The field width determines the number of bits in the field.

Condition Codes:
N    Set if the most significant bit of the field is set, otherwise cleared
Z    Set if all bits of the field are zero, otherwise cleared
V    Always cleared
C    Always cleared
X    Not affected

This instruction is not supported by CPU32 based microcontrollers.

    

	Allowable Addressing Modes

	BFEXTU	Dn{offset:width},Dn
	BFEXTU	(An){offset:width},Dn
	BFEXTU	(d16,An){offset:width},Dn
	BFEXTU	(d8,An,Xn){offset:width},Dn
	BFEXTU	(bd,An,Xn){offset:width},Dn
	BFEXTU	([bd,An,Xn],od){offset:width},Dn
	BFEXTU	([bd,An],Xn,od){offset:width},Dn
	BFEXTU	(xxx).W{offset:width},Dn
	BFEXTU	(xxx).L{offset:width},Dn
	BFEXTU	(d16,PC),Dn
	BFEXTU	(d8,PC,Xn),Dn
	BFEXTU	(bd,PC,Xn),Dn
	BFEXTU	([bd,PC,Xn],od),Dn
	BFEXTU	([bd,PC],Xn,od),Dn

where:

offset specifies the starting bit of the field and is either a data register Dn or an expression having a value from 0 to 31.

width specifies the width of the field and is either a data register Dn or an expression having a value from 0 to 31 where 1 to 31 specify field widths of 1 to 31 and 0 specifies a field width of 32.