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MICROPROCESSOR INSTRUCTION REFERENCE->SRL m
SRL m Logical shift operand s right
0 -> bit7->.....-> bit0 -> CY
Flags
| S | Set if result -ve, else cleared |
| Z | Set if result zero, else cleared |
| H | Cleared |
| P/V | Set if parity even, else cleared |
| N | Cleared |
| C | Set to bit 0 of source data |
| m: | No of | M | T | usec @ |
| bytes | cycles | states | 2 MHz |
| r | 2 | 2 | 8 | 4 |
| (HL) | 2 | 4 | 15 | 7.5 |
| (IX+d) | 4 | 6 | 23 | 11.5 |
| (IY+d) | 4 | 6 | 23 | 11.5 |