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MICROPROCESSOR INSTRUCTION REFERENCE->LSLD

LSLD    Logical shift left double accumulator  (same as ASLD)

C <-   ACC A   <-   ACC B   <- 0
   b7       b0  b7       b0

Condition Code Register:

C  Set to bit 7 of operand (Acc A)
V  Set if N 'eor' C = 1 after execution, else cleared
Z  Set if result Zero, else cleared
N  Set if result Negative, else cleared
I  Not affected
H  Not affected


    

Addressing mode	Assembler syntax
Implied:	LSLD