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MICROPROCESSOR INSTRUCTION REFERENCE->SWI

SWI    Software interrupt
SWI2
SWI3

SWI:  PC <- (&FFFA):(&FFFB)
SWI2: PC <- (&FFF4):(&FFF5)
SWI3: PC <- (&FFF2):(&FFF3)

Condition Code Register:
    

	SWI	SWI2 and SWI3
E	Always set	Always set
F	Set always	Not affected
H	Not affected	Not affected
I	Set always	Not affected
N	Not affected	Not affected
Z	Not affected	Not affected
V	Not affected	Not affected
C	Not affected	Not affected

    

Addressing mode	No of cycles	No of bytes
Implied:	19 (20)	1 (2)

Bracketed values are for SWI2 and SWI3