// Embedded Development Studio identification info, do not remove:
//{{EDS_STDFILE(CF5282SC.C)
//}}EDS_STDFILE

#define _DEFSYMS
#include "xstdsys.h"

// The chip and dram initialisation sequences below are for illustrative
// purposes only.  They must be modified to suit your target system.

void _init_chip()
{
	// Note that this function is called before any C variables have been initialised.
	// It is not called if 'Code and data in RAM' is checked in the linker settings

	//{{EDS_CONFIG(WATCHDOG)
	g_pWATCHDOG->WCR = 0;
	//}}EDS_CONFIG

	//{{EDS_CONFIG(OSCILLATORS)
	// External oscillator frequency: 8000000
	g_pCLOCK->SYNCR &= ~SYNCR_RFD0;
	//}}EDS_CONFIG

	//{{EDS_CONFIG(GPIO)
	g_pGPIO->PASPAR = 0XF0;
	//}}EDS_CONFIG

	//{{EDS_CONFIG(CHIPSELECTS)
	//}}EDS_CONFIG

	//{{EDS_CONFIG(DRAM)
	//}}EDS_CONFIG

}

void _init_chip1()
{
	// This function is called after the C variables have been initialised, just before the call to main
	// It is always called whatever the linker settings

	//{{EDS_CONFIG(UART0)
	//}}EDS_CONFIG

	//{{EDS_CONFIG(UART1)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(UART2)
	//}}EDS_CONFIG

	//{{EDS_CONFIG(PIT0)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(PIT1)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(PIT2)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(PIT3)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(GPTA)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(GPTB)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(QADC)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(QSPI)
	//}}EDS_CONFIG
	
	//{{EDS_CONFIG(CAN)
	for (unsigned int nMsgObj = 0; nMsgObj < 16; nMsgObj++)
	{
	    g_pCAN->MBUFF[nMsgObj].CONTROL_STATUS = 0X00;
	}
	g_pCAN->CANCTRL0 = CANCTRL0_BOFFMSK | CANCTRL0_ERRMSK;
	g_pCAN->CANCTRL1 = CANCTRL1_PROPSEG2 | CANCTRL1_PROPSEG0;
	g_pCAN->CANCTRL2 = CANCTRL2_RJW1 | CANCTRL2_RJW0 | CANCTRL2_PSEG11 | CANCTRL2_PSEG10 | CANCTRL2_PSEG22;
	g_pCAN->PRESDIV = 0X0F;
	g_pCAN->IMASK = IMASK_BUF1M | IMASK_BUF0M;
	g_pCAN->MBUFF[0].CONTROL_STATUS = 0X40;
	g_pCAN->MBUFF[0].ID_HIGH = 0X20;
	g_pCAN->MBUFF[0].ID_LOW = 0X00;
	g_pCAN->MBUFF[1].CONTROL_STATUS = 0XC8;
	g_pCAN->MBUFF[1].ID_HIGH = 0X40;
	g_pCAN->MBUFF[1].ID_LOW = 0X00;
	g_pCAN->MBUFF[1].DATA[0] = 0X01;
	g_pCAN->MBUFF[1].DATA[1] = 0X02;
	g_pCAN->MBUFF[1].DATA[2] = 0X03;
	g_pCAN->MBUFF[1].DATA[3] = 0X04;
	g_pCAN->MBUFF[1].DATA[4] = 0X05;
	g_pCAN->MBUFF[1].DATA[5] = 0X06;
	g_pCAN->MBUFF[1].DATA[6] = 0X07;
	g_pCAN->MBUFF[1].DATA[7] = 0X08;
	g_pINTERRUPT1->ICR[8] = ICR_IL0;
	g_pINTERRUPT1->ICR[9] = ICR_IL0;
	g_pINTERRUPT1->ICR[24] = ICR_IL0;
	g_pINTERRUPT1->ICR[25] = ICR_IL0;
	g_pINTERRUPT1->IMRL = 0XFCFFFCFE;
	g_pCAN->CANMCR = CANMCR_SUPV;
	//}}EDS_CONFIG

	//{{EDS_CONFIG(SMBUS0)
	//}}EDS_CONFIG

	//{{EDS_CONFIG(CACHE)
	//}}EDS_CONFIG
}